ICs having multiple dies or chips made in a single package increase the capacity of the package without substantially increasing the overall size or dimension of the package. In one example, two or more memory chips may be encapsulated in a single package so as to double or increase the memory capacity of the package without doubling or multiplying the physical size/dimension of the package.
One approach is disclosed in U.S. Pat. No. 6,498,391 namely, a dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a package. According to this patent, both chips are mounted to a leadframe simply by an insulative adhesive layer covering the full mounting area of each chip.
Mounting a chip onto a leadframe in the above manner may cause problems. For example, since the adhesive is formed as a layer between the leadframe and each chip, there left voids, gaps and/or cavities between the lead portions, which are sandwiched between the adhesive layers. These voids, gaps and/or cavities, within which air may be trapped, are sources of potential device failure.
In view of the foregoing, it is desirable to provide an Integrated Circuits package structure having stacked dies and method of manufacturing of the same, so that to at least partly overcome the drawbacks mentioned above.